1. Field of the Invention
The present invention relates to a method for forming an isolation region providing an isolation between neighboring elements in making a semiconductor device, and more particularly to a method for forming such an isolation region using a trench.
2. Description of the Prior Art
A method for forming an isolation region using a trench in the manufacture of a complementary metal oxide semiconductor (CMOS) has been known in the technical field and is illustrated in FIGS. 3A to 3G. Such a method will now be described, in conjunction with the drawings.
As shown in FIG. 3A, on a p type silicon substrate 21, a pad oxide film 22 and a nitride film 23 are deposited in this order, using a chemical vapor deposition (CVD) method. Using a photoresist 24 formed on the nitride film 23, a trench region is defined at the nitride film 23.
Using the photoresist 24 as a mask, the nitride film 23 and the oxide film 22 are then subjected to a dry etching, to remove their portions corresponding to the trench region and thus form a trench window, as shown in FIG. 3B. The p type silicon substrate 21 is also subjected to the dry etching using the photoresist 24 as a mask, so as to form a trench at a region located beneath the surface of the p type silicon substrate 21.
Following a removal of the photoresist 24, a polysilicon film 25 is deposited on the entire exposed surface, as shown in FIG. 3C. The polysilicon film 25 is made of polysilicon doped with p type impurity ions such as boron ions and serves as a diffusion source for n type channel stop ions.
Thereafter, a photoresist 26a is formed on a desired portion of the polysilicon film 25, to define an n type well region in the substrate 21. Such an n type well region is needed for providing a p type metal oxide semiconductor (PMOS). Using the photoresist 26a as a mask, the polysilicon 25 is then dry etched to remove its portion corresponding to the defined n type well region. using the photoresist 26a as a mask again, n type impurity ions are slantly implanted in the n type well region. By an annealing process, the implanted impurity ions are diffused to obtain an n type well for the PMOS.
The photoresist 26 is then removed, as shown in FIG. 3E. The polysilicon film 25 remaining in an n type metal oxide semiconductor (NMOS) region is then subjected to an annealing process so that p type boron ions doped in the polysilicon film 25 are diffused, thereby forming a p type channel stop layer 28 at a region located beneath a surface portion of the trench corresponding to the NMOS region, as shown in FIG. 3F.
As shown in FIG. 3F again, the polysilicon film 25 is then removed and an oxide film 29 is thermally formed in the trench. For providing an isolation region, an oxide film 30 is then deposited on the entire exposed surface, using the CVD method. This deposition is carried out such that the trench is completely filled with the oxide film 30. However, a groove is formed on the oxide film 30 above the trench. This groove is filled with a smoothing polymer 31, so as to make the surface of the oxide film 30 smooth.
Subsequently, the oxide film 30 including the polymer 31 is etched backed from its surface to the surface of nitride film 23 using a dry etch process, thereby forming a surface-smoothed element isolating region 30a, as shown in FIG. 3G.
However, the above-mentioned prior art has the following problems.
First, since the p type silicon substrate is vertically etched back using the dry etch process to form the trench therein, it is likely to generate crystal defects in the substrate at bottom and side portions of the trench.
Second, the depth of trench is varied depending on the pattern size in each element isolating region, thereby varying the size of the groove which is formed when the oxide film is deposited to fill the trench. As a result, a step referred to as a micro loading effect occurs between neighboring isolation regions.